位于上海市, c23的 2 个优质support and deployment engineer职位（正在招聘！）

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Lead Design Engineer (Virtual Solution)
Cadence Design Systems —上海市
RTL design experience (SystemVerilog / Verilog). Support customer enablement, including bring-up, debug, and solution deployment.
5 小时
Lead Design Engineer(Virtual Solution)
Cadence Design Systems —上海市
RTL design experience (SystemVerilog / Verilog). Support customer enablement, including bring-up, debug, and solution deployment.
5 小时

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Key Responsibilities

Design and develop system-level AVIP solutions for emulation/prototyping platforms (Palladium, Protium)
Build and integrate Accelerated Verification IP environments for complex SoC and subsystem validation
Develop end-to-end verification flows including:
- AVIP integration
- Testbench and system modeling
- Bare-metal / driver-level validation
Optimize solutions for performance, scalability, and emulation efficiency
Develop custom test cases, tools, and automation to enable advanced use models (embedded / co-emulation / hybrid flows)
Work closely with cross-functional teams (PE, AE, customers) to debug and resolve system-level issues
Support customer enablement, including bring-up, debug, and solution deployment

Required Qualifications

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with at least 3 years’ experience
Strong expertise in high-speed protocols such as:
- PCIe, CXL, AMBA, UCIe, Ethernet (at least one)
RTL design experience (SystemVerilog / Verilog)
C/C++ development experience for modeling, testbench, or system integration
Hands-on experience with Palladium / Protium / FPGA / emulation platforms is strongly preferred
Good debugging skills for complex system integration issues

Preferred Qualifications

Soft Skills