Hands on experience to lead PDK team or develop projects. Direct major foundries professional background is a plus
Deep understanding of analog design flows, including circuit and layout design, physical verification (DRC/LVS/Dummy Fill), and post‑layout RC extraction flows
Proficient in program/script languages, including PERL/TCL/SKILL., experience w/ Cadence PAS/Pcell Designer tool is desired.
Solid understanding of Spice models and simulation flows is required.
Bachelor with 15+ years’ related working experience. MS+ is a plus.