Job Description
We are seeking highly motivated and talented engineers with strong C++ development skills and a deep interest in advanced‑node integrated circuit design.
In this role, you will contribute to the development of a high‑performance, multi‑threaded, distributed geometry layout engine within the INNOVUS NanoRoute system, including next‑generation GPU‑accelerated DRC capabilities.
You will collaborate closely with a global R&D team to design, implement, and optimize core algorithms that drive industry‑leading P&R tools.
Responsibilities
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Design and develop core components of a multi-threaded, distributed geometry layout engine.
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Implement efficient data structures and algorithms for large‑scale physical design challenges.
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Develop, optimize, and maintain CUDA‑based GPU kernels for DRC and geometric computation.
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Analyze and optimize performance across CPU/GPU boundaries, including memory transfers and kernel execution.
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Work with cross‑functional global teams to define technical specifications and project scope.
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Debug, optimize, and maintain production-quality C++ code in a Linux environment.
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Collaborate with internal stakeholders and customers to understand requirements and deliver high‑quality solutions.
Minimum Qualifications
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MS in CS/EE or BS with 2+ years of relevant experience.
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C/C++ software development experience in Linux environment.
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Solid understanding and practical use of data structures and algorithms.
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Self‑motivated with excellent problem‑solving skills.
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Ability to write clear technical specifications and accurately estimate development effort.
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Strong communication skills and comfort interacting with global customers or internal partners.
Preferred
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Experience with multi-threaded programming.
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Knowledge of physical design algorithms.
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Knowledge of NVIDIA GPU architecture.
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Prior R&D experience with IC physical design tools.
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Hands‑on experience with physical design flows (Floorplanning, Placement, Routing, CTS).
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Experience with Tcl or other scripting languages.
