1. Responsible for Low Power IP design delivery (AVS, Dvfs Handler, etc.) 2. Responsible for SOC Low Power design delivery (Power Tree, UPF, Low Power Control, Thermal Control, etc.) 3. Participate in the definition of SOC power consumption scenarios and Power Target decomposition 4. Cooperate with designers to complete chip Power Optimization and Power Signoff 5. Participate in building Power Model.
1. Electronics, microelectronics, computer related majors, more than 2 years of SOC design experience 2. Familiar with SOC design process and methodology Low Power or Thermal delivery experience is a plus 3. Familiar with RTL design, proficient in using EDA tools such as Synopsys/Cadence/Mentor Low Power IP or UPF design experience is a plus 4. Familiar with ASIC Power analysis and optimization methods experience in Power Simulation or Correlation is a plus 5. Work conscientiously and responsibly, have good cross-department communication and learning abilities, and good teamwork spirit.
